Compositions and methods for planarizing or polishing the surface of a substrate, especially for chemical-mechanical polishing (CMP), are well known in the art. Polishing compositions (also known as polishing slurries) used in CMP processes typically contain an abrasive material in an aqueous solution, and are applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. Typical abrasive materials include aluminum oxide, cerium oxide, silicon dioxide, and zirconium oxide. The polishing composition is generally used in conjunction with a polishing pad (e.g., polishing cloth or disk). The polishing pad may contain abrasive material in addition to, or instead of, the abrasive material in the polishing composition.
Polishing compositions for silicon dioxide based inter-metal dielectric layers have been particularly well developed in the semiconductor industry, and the chemical and mechanical nature of polishing and wear of the silicon dioxide based dielectrics is reasonably well understood. One problem with the silicon dioxide-based dielectric materials, however, is that their dielectric constant is relatively high, being approximately 3.9 or higher, depending on factors such as residual moisture content. As a result, the capacitance between the conductive layers is also relatively high, which in turn limits the speed (frequency) at which a circuit can operate. Strategies being developed to increase the frequency at which the circuit can operate include (1) incorporating metals with lower resistivity values (e.g., copper), and (2) providing electrical isolation with insulating materials having lower dielectric constants relative to silicon dioxide.
One way to fabricate planar copper circuit traces on a dielectric substrate is referred to as the damascene process. In accordance with this process, the silicon dioxide dielectric surface is patterned by a conventional dry etch process to form holes (i.e., vias) and trenches for vertical and horizontal interconnects prior to deposition of copper onto the surface. Copper has the property of being a fast diffuser and can move quickly through the underlying dielectric layer to “poison” the device. Thus, a diffusion barrier layer is typically applied to the substrate before deposition of copper. The diffusion barrier layer is provided with a copper seed layer and then over-coated with a copper layer from a copper plating bath. Chemical-mechanical polishing is employed to reduce the thickness of the copper over-layer, as well as the thickness of the diffusion barrier layer, until a planar surface that exposes elevated portions of the dielectric surface is obtained. The vias and trenches remain filled with electrically conductive copper forming the circuit interconnects.
Tantalum and tantalum nitride have found wide acceptance in the industry as barrier layer materials and are typically applied to a substrate by physical vapor deposition (PVD). However, as the lines defining circuits are being reduced in size to the 65 nm and 45 nm scale, one concern is to avoid degrading the current carrying capacity of the copper lines. As the dimensions of copper lines are reduced, electron scattering from the lines becomes significant and causes an increase in resistivity. One solution is to reduce the thickness of the barrier layer and thereby allow for a proportionately thicker copper line within a given trench by using an atomic layer deposited (ALD) barrier layer. A copper seed layer is then applied by a conventional PVD process. However, formation of the copper seed layer is complicated by the need to provide a precise thickness of the layer to avoid overhang at the top of trenches with overly thick layers and to avoid copper oxidation by atmospheric oxygen occurring with overly thin layers.
One proposed solution is to plate copper directly onto a diffusion barrier. Ruthenium, in particular, has shown promise in this application. The insolubility of copper in ruthenium makes ruthenium suitable for use as a diffusion barrier, and the electrical conductivity of ruthenium allows for direct plating of copper onto the ruthenium, which obviates the need for a copper seed layer. Although the possibility of replacing tantalum/tantalum nitride barriers layers with ruthenium remains an attractive possibility, the likely course of development appears to lie with a copper-ruthenium-tantalum/tantalum nitride system.
Polishing compositions that have been developed for ruthenium and other noble metals typically contain strong oxidizing agents, have a low pH, or both. Copper tends to oxidize very rapidly in these polishing compositions. Additionally, because of the difference in standard reduction potentials of ruthenium and copper, copper suffers from galvanic attack by ruthenium in the presence of conventional ruthenium polishing compositions. The galvanic attack leads to etching of copper lines and a resulting degradation of circuit performance. Further, the wide difference in chemical reactivity of copper and ruthenium in conventional polishing compositions results in widely differing rates of removal in chemical-mechanical polishing of substrates containing both metals, which can result in overpolishing of copper.
Finally, substrates comprising tantalum or tantalum nitride in addition to ruthenium and copper pose additional challenges in that polishing compositions suitable for ruthenium or copper, themselves highly dissimilar materials, are typically unsuitable for the polishing of tantalum or tantalum nitride layers. Successful implementation of ruthenium-copper-tantalum microelectronic technology would require new polishing methods suitable for polishing of all three materials.
Thus, there remains a need in the art for improved polishing compositions and methods for chemical-mechanical polishing of substrates comprising ruthenium and copper and optionally tantalum or tantalum nitride.